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THS8134TQFP Datasheet(PDF) 6 Page - Texas Instruments |
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THS8134TQFP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 24 page THS8134, THS8134A, THS8134B TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION SLVS205D – MAY 1999 – REVISED MARCH 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 2. INS3_INT/M2_INT Selection on M2 LAST EVENT ON SYNC SYNC_T M1 M2 (see Note 2) DESCRIPTION H →L L or H X INS3_INT Sync insertion active: SYNC low enables sync generation on 1 (INS3_INT=L) or all 3 (INS3_INT=H) DAC outputs. SYNC_T determines the sync polarity. L →H X X M2_INT Device mode programming active: The DAC outputs reflect the DAC inputs (BLANK=H) or are forced to the blanking level (BLANK=L). M2 is interpreted according to Table 1. X = Don’t care NOTE 2: M1 and M2 start configuring the device as soon as they are interpreted, which is continuously for M1 (static pin) or on the second rising edge on CLK after a transition on SYNC for M2. M2 is interpreted as either INS3_INT or M2_INT, as shown in Table 2. programming example Configuration of the device will normally be static in a given application. If M2_INT and INS3_INT need to be both low or high, the M2 pin is simply tied low or high. If M2_INT and INS3_INT need to have different levels, these can be easily derived from the signal on the SYNC pin, as shown in Table 3 and Figure 2. Table 3. Generating M2 From SYNC In order to have: Apply to M2: M2_INT INS3_INT Apply to M2: L H ...SYNC delayed by 2 CLK periods H L ...inverted SYNC delayed by 2 CLK periods The input formats and latencies are shown in Figures 3–5 for each operation mode. CLK SYNC M2 [=SYNC_delayed] INS3_INT M2_INT M2 [=NOT SYNC_delayed] INS3_INT M2_INT if (M2 = SYNC_delayed) ⇒ M2_INT = L and INS3_INT = H) if (M2 = NOT SYNC_delayed) ⇒ M2_INT = H and INS3_INT = L) Figure 2. Generating INS3_INT and M2_INT from M2 |
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