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THS8133A Datasheet(PDF) 3 Page - Texas Instruments |
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THS8133A Datasheet(HTML) 3 Page - Texas Instruments |
3 / 23 page THS8133, THS8133A, THS8133B TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME PIN I/O DESCRIPTION RPr0–PRr9 13–22 I Red or Pr pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for different operating modes SYNC 24 I Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output (INS3_INT=L, see terminal M2) or ARPr, AGY and ABPb outputs (INS3_INT=H, see terminal M2) are driven to the sync level, irrespective of the values on the data or BLANK inputs. Consequently, SYNC should remain low for the whole duration of sync, which is in the case of a tri-level sync both the negative and positive portion (see Figure 7). SYNC_T 25 I Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted, a positive sync (higher than blanking level) is generated when SYNC is low. When disabled, a negative sync (lower than blanking level) is generated when SYNC is low. When generating a tri-level (negative-to-positive) sync, a L → H transition on this signal positions the start of the positive transition. See Figure 6 for timing control. The value on SYNC_T is ignored when SYNC is not asserted (high). VREF 37 I/O Voltage reference for DACs. An internal voltage reference of nominally 1.35 V is provided, which requires an external 0.1 µF ceramic capacitor between VREF and AVSS. However, the internal reference can be overdriven by an externally supplied reference voltage. R/Pr Register ARPr RPr[9:0] DAC G/Y Register B/Pb Register DAC DAC DVDD Configuration Control SYNC/BLANK Control Bandgap Reference GY[9:0] BPb[9:0] CLK M1 M2 AGY ABPb DVSS COMP VREF AVDD AVSS SYNC BLANK FSADJ SYNC_T Input Formatter Figure 1. THS8133 Block Diagram |
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