TCM29C18, TCM29C19, TCM129C18, TCM129C19

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

11

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Time Slot

td(TSDX)

tpd9

FSX

DCLKX

CLKX

PCM OUT

12

3

4

5

67

8

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

td(FSX)

tpd6

tpd8

tpd7

NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is

indicated.

B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.

Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.

C. All timing parameters referenced to VIH and VIL except tpd7 and tpd8, which references the high-impedance state.

Figure 5. Transmit Timing (Variable-Data Rate)

FSR

DCLKR

CLKR

PCM IN

1

2

34

56

7

8

td(TSDR)

td(FSR)

tsu(PCM IN)

th(PCM IN)

tSER

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Don’t Care

NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is

indicated.

B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.

Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.

C. All timing parameters referenced to VIH and VIL except tpd7 and tpd8, which references the high-impedance state.

Figure 6. Receive Timing (Variable-Data Rate)