SN751177, SN751178

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS

SLLS059D – FEBRUARY 1990 – REVISED MAY 1999

6

POST OFFICE BOX 655303

DRIVER SECTIONS

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

Input clamp voltage

II = –18 mA

–1.5

V

VOH

High-level output voltage

VIH = 2 V,

VIL = 0.8 V,

IOH = –33 mA

3.7

V

VOL

Low-level output voltage

VIH = 2 V,

VIL = 0.8 V,

IOH = 33 mA

1.1

V

|VOD1|

Differential output voltage

IO = 0

1.5

6

V

RL = 100 Ω

See Figure 1

2 or

|VOD2|

Differential output voltage

RL = 100 Ω,

See Figure 1

1/2 VOD1‡

V

OD2

g

RL = 54 Ω,

See Figure 1

1.5

5

VOD3

Differential output voltage

See Note 4

1.5

5

V

∆|VOD|

Change in magnitude of

differential output voltage (see Note 5)

±0.2

V

VOC

Common-mode output voltage

RL = 54 Ω or 100 Ω,

See Figure 1

–1§

3

V

∆|VOC|

Change in magnitude of

common-mode output voltage (see Note 5)

±0.2

V

IO

Output current with power off

VCC = 0,

VO = –7 V to 12 V

±100

µA

IOZ

High-impedance-state output current

VO = –7 V to 12 V

±100

µA

IIH

High-level input current

VIH = 2.7 V

20

µA

IIL

Low-level input current

VIL = 0.4 V

–100

µA

VO = –7 V

–250

IOS

Short-circuit output current (see Note 6)

VO = VCC

250

mA

VO = 12 V

250

ICC

Supply current

No load

Outputs enabled

80

110

mA

ICC

Supply current

No load

Outputs disabled

50

80

mA

† All typical values are at VCC = 5 V and TA = 25°C.

‡ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.

§ The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode

output and threshold voltage levels only.

NOTES:

4. See TIA/EIA-485-A Figure 3.5, Test Termination Measurement 2

5.

∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high

level to a low level.

6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(OD)

Differential output delay time

RL =54 Ω

See Figure 3

20

25

ns

tt(OD)

Differential output transition time

RL = 54 Ω,

See Figure 3

27

35

ns

tPLH

Propagation delay time, low- to high-level output

RL =27 Ω

See Figure 4

20

25

ns

tPHL

Propagation delay time, high- to low-level output

RL = 27 Ω,

See Figure 4

20

25

ns

tPZH

Output enable time to high level

RL = 110 Ω,

See Figure 5

80

120

ns

tPZL

Output enable time to low level

RL = 110 Ω,

See Figure 6

40

60

ns

tPHZ

Output disable time from high level

RL = 110 Ω,

See Figure 5

90

120

ns

tPLZ

Output disable time from low level

RL = 110 Ω,

See Figure 6

30

45

ns