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SN74LVC823APWT Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC823APWT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 14 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) To Eight Other Channels 1D 1Q CLKEN CLK OE CLR 1 11 14 13 2 R 1D C1 23 SN74LVC823A 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS305I – MARCH 1993 – REVISED FEBRUARY 2005 A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (EACH FLIP-FLOP) INPUTS OUTPUT Q OE CLR CLKEN CLK D L L X X X L L H L ↑ H H L H L ↑ L L L H H X X Q0 H X X X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
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