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SN74F126 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74F126 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 5 page SN74F126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS017A – D3212, JANUARY 1989 – REVISED OCTOBER 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 2–1 • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output enable (OE) input is low. The SN74F126 is characterized for operation from 0 °C to 70°C. FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A Y H H H H LL L X Z logic symbol† logic diagram (positive logic) EN 1 1OE 2 1A 1Y 3 4 2OE 5 2A 10 3OE 9 3A 13 4OE 12 4A 2Y 6 3Y 8 4Y 11 1 4 56 2A 2Y 2OE 1 23 1A 1Y 1OE 10 98 3A 3Y 3OE 13 12 11 4A 4Y 4OE † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. D OR N PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1OE 1A 1Y 2OE 2A 2Y GND VCC 4OE 4A 4Y 3OE 3A 3Y PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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