Intelligent Graphics Display

AND1741MST

Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085

3

Tel: 408.523.8200 • Fax: 408.733.1287 • sales@purdyelectronics.com • www.purdyelectronics.com

7/20/07

Power Supply

compensation.

Timing Relationships and Diagram

Timing Diagram

Block Diagram

Temperature Variations

Temperature

V

V

0°C

21.0

20.0

+25°C

19.5

18.5

+50°C

17.6

16.6

Signal Timing Relationships

Item

Symbol

Min.

Max.

Unit

C/D Set Up Time

100

–

ns

C/D Hold Time

10

–

CE

Pulse Width

80

–

Data Set Up Time

80

–

Data Hold Time

40

–

Access Time

–

150

Output Hold Time

10

50

t

CDS

t

t

ACC

t

CDH

t

DH

t

OH

t

DS

C/D

CE

RD, WR

D0-D7

(WRITE)

D0-D7

(READ)

80

80

X-Driver

80

X-Driver

64

Y-Driver

64

Y-Driver

Control Lines

ED

HSCP

FR

LP

CDATA

13

8

8

R/W

CE1

WR

D0-D7

RD

CE

C/D

RESET

LCD

V

FL

V

FL

Backlight

X-Driver

I/O0-I/O7

A0-A12

AD0-AD12

D0-D7

RAM

(8K byte)

T6963C

Because signal lines are directly connected

to C-MOS and are not pull-up or pull-down

internally, except RESET which is pull-up to

V

external noise.