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SN74ALVCH16903DGG Datasheet(PDF) 3 Page - Texas Instruments |
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SN74ALVCH16903DGG Datasheet(HTML) 3 Page - Texas Instruments |
3 / 12 page SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables (Continued) PARI/O FUNCTION† INPUTS OUTPUT PAROE Σ OF INPUTS 1A – 10A = H APAR OUTPUT PARI/O L 0, 2, 4, 6, 8, 10 L L L 1, 3, 5, 7, 9 L H L 0, 2, 4, 6, 8, 10 H H L 1, 3, 5, 7, 9 H L H X X Z † This table applies to the first device of a cascaded pair of ALVCH16903 devices. logic diagram (positive logic) 13 8 (1A–8A) 13 5 (9A–12A, APAR) Flip-Flop 13 Flip-Flop 5 13 DQ Parity Check 12 11 DQ DQ XOR DQ APAR APAR 10 (1A–10A) (1A–11A/YERREN, APAR) 12 (1A–12A) 11A/YERREN 12 1 33 56 29 28 36 30 OE MODE CLK CLKEN 1A–12A, APAR PAROE PARI/O YERR 1Y2–12Y2 1Y1–12Y1 |
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