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LTC2216CUP Datasheet(PDF) 1 Page - Linear Technology |
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LTC2216CUP Datasheet(HTML) 1 Page - Linear Technology |
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1 / 36 page  LTC2216/LTC2215 1 22165f TYPICAL APPLICATION APPLICATIONS 16-Bit, 80Msps/65Msps Low Noise ADC The LTC®2216/LTC2215 are 80Msps/65Msps sampling 16- bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P. The LTC2216/LTC2215 are perfect for demanding com- munications applications, with AC performance that includes 81.5dBFS noise floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specs include ±3.5LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycles. n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE n Sample Rate: 80Msps/65Msps n 81.5dBFS Noise Floor n 100dB SFDR n SFDR >95dB at 70MHz n 85fsRMS Jitter n 2.75VP-P Input Range n 400MHz Full Power Bandwidth S/H n Optional Internal Dither n Optional Data Output Randomizer n LVDS or CMOS Outputs n Single 3.3V Supply n Power Dissipation: 970mW/700mW n Clock Duty Cycle Stabilizer n Pin-Compatible with LTC2208, LTC2217 n 64-Pin (9mm × 9mm) QFN Package , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. LTC2216: 64k Point FFT, fIN = 4.9MHz, –1dBFS – + S/H AMP CORRECTION LOGIC AND SHIFT REGISTER OUTPUT DRIVERS 16-BIT PIPELINED ADC CORE INTERNAL ADC REFERENCE GENERATOR 1.575V COMMON MODE BIAS VOLTAGE CLOCK/DUTY CYCLE CONTROL D15 • • • D0 SHDN DITH MODE LVDS RAND VCM ANALOG INPUT 22165 TA01 CMOS OR LVDS 0.5V TO 3.6V 3.3V 3.3V SENSE OGND OVDD 2.2μF 1μF 1μF 1μF 1μF VDD GND ADC CONTROL INPUTS AIN+ ENC + AIN– ENC – OF CLKOUT FEATURES DESCRIPTION 22165 TA01b –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 010 20 30 40 FREQUENCY (MHz) |
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