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LTC2216IUP-PBF Datasheet(PDF) 6 Page - Linear Technology |
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LTC2216IUP-PBF Datasheet(HTML) 6 Page - Linear Technology |
6 / 36 page LTC2216/LTC2215 6 22165f POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS LTC2215 LTC2216 UNITS MIN TYP MAX MIN TYP MAX VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD 17 17 mW Standard LVDS Output Mode OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 3 3.3 3.6 V IVDD Analog Supply Current l 217 290 300 370 mA IOVDD Output Supply Current l 75 90 75 90 mA PDIS Power Dissipation l 964 1254 1240 1518 mW Low Power LVDS Output Mode OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 3 3.3 3.6 V IVDD Analog Supply Current l 215 290 298 370 mA IOVDD Output Supply Current l 42 50 42 50 mA PDIS Power Dissipation l 848 1122 1120 1386 mW CMOS Output Mode OVDD Output Supply Voltage (Note 8) l 0.5 3.6 0.5 3.6 V IVDD Analog Supply Current l 212 290 295 370 mA PDIS Power Dissipation l 700 957 970 1220 mW SYMBOL PARAMETER CONDITIONS LTC2215 LTC2216 UNITS MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Note 8) l 1 65 1 80 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l 7.31 5 7.692 7.692 500 500 5.94 4.06 6.25 6.25 500 500 ns ns tH ENC High Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l 7.31 5 7.692 7.692 500 500 5.94 4.06 6.25 6.25 500 500 ns ns LVDS Output Mode (Standard and Low Power) tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 1.3 2.5 3.8 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns tRISE Output Rise Time 0.5 0.5 ns tFALL Output Fall Time 0.5 0.5 ns Data Latency Data Latency 7 7 Cycles CMOS Output Mode tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS Demuxed 7 7 7 7 Cycles Cycles |
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