SN74ALS164A

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER

SDAS159D – APRIL 1982 – REVISED DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

Small-Outline (D) Packages and Standard

Plastic (N) 300-mil DIPs

description

This 8-bit parallel-out serial shift register features

AND-gated serial (A and B) inputs and an

asynchronous clear (CLR) input. The gated serial

inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets

the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which

determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,

provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition

of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.

The SN74ALS164A is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS†

CLR

CLK

A

B

QA

QB ...QH

L

X

X

X

L

L

L

H

LX

X

QA0

QB0

QH0

H

↑

HH

H

QAn

QGn

H

↑

LX

L

QAn

QGn

H

↑

X

L

L

QAn

QGn

† QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,

before the indicated steady-state input conditions were

established.

H = high level (steady state), L = low level (steady state)

X = irrelevant (any input, including transitions)

↑ = transition from low to high level

QAn, QGn = the level of QA or QG before the most recent

↑ transition of the clock; indicates a 1-bit shift.

D OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

A

B

GND

CLR

CLK

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.