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NCV70521 Datasheet(PDF) 6 Page - ON Semiconductor |
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NCV70521 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 28 page AMIS−30521, NCV70521 http://onsemi.com 6 Table 5. DC PARAMETERS (DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit SUPPLY INPUTS VBB VBB Nominal Operating Supply Range 6 30 V IBB Total Current Consumption Unloaded Outputs 8 mA IBBS Sleep Current in VBB (Note 7) Unloaded Outputs 100 mA VDD VDD Logic Supply Voltage 4.75 5 5.25 V IDDD Dynamic Current (Note 6) 7.5 10 mA IDDS Sleep Current in VDD (Note 7) 100 mA POWER ON RESET (POR) VDDH VDD Internal POR Comparator Threshold VDD Rising 3.85 4.20 4.55 V VDDL Internal POR Comparator Threshold VDD Falling 3.85 V VDDHYS Hysteresis Between VDDH and VDDL 0.10 0.35 0.60 V MOTOR DRIVER IMDmax,Peak MOTXP MOTXN MOTYP MOTYN Max Peak Current Through Motor Coil TJ = −40°C 1600 mA IMDabs Absolute Error on Coil Current TJ = 125°C −10 10 % IMDrel Error On Current Ratio Icoilx/Icoily −7 7 % ISET_TC1 Temperature Coefficient of Coil Current Set−Level, CUR[4:0] = 0...27 TJ v 160°C −240 ppm/K ISET_TC2 Temperature Coefficient of Coil Current Set−Level, CUR[4:0] = 28...31 TJ v 160°C −490 ppm/K RHS On−Resistance High−Side Driver, (Note 9) CUR[4:0] = 0...31 VBB = 12 V, TJ = 27°C 0.45 0.56 W VBB = 12 V, TJ = 160°C 0.94 1.25 W RLS3 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 23...31 VBB = 12 V, TJ = 27°C 0.45 0.56 W VBB = 12 V, TJ = 160°C 0.94 1.25 W RLS2 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 16...22 VBB = 12 V, TJ = 27°C 0.90 1.2 W VBB = 12 V, TJ = 160°C 1.9 2.5 W RLS1 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 9...15 VBB = 12 V, TJ = 27°C 1.8 2.3 W VBB = 12 V, TJ = 160°C 3.8 5.0 W RLS0 On−Resistance Low−Side Driver, (Note 9) CUR[4:0] = 0...8 VBB = 12 V, TJ = 27°C 3.6 4.5 W VBB = 12 V, TJ = 160°C 7.5 10 W IMpd Pulldown Current HiZ Mode 1 mA DIGITAL INPUTS Ileak DI, CLK NXT, DIR CLR, CS Input Leakage (Note 8) TJ = 160°C 0.5 mA VIL Logic Low Threshold 0 0.75 V VIH Logic High Threshold 2.20 VDD V Rpd_CLR CLR Internal Pulldown Resistor 120 280 kW Rpd_TST TST0 Internal Pulldown Resistor 3 8 kW 6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Guaranteed by design. 7. Current with all analogue cells in power down. Logic is powered but no clocks running. All outputs unloaded, no inputs floating. 8. Not valid for pins with internal Pulldown resistor 9. Characterization Data Only |
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