SN54LVTH573, SN74LVTH573

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS687E – MAY 1997 – REVISED APRIL 1999

1

POST OFFICE BOX 655303

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

(5-V Input and Output Voltages With

Down to 2.7 V

Insertion

Need for External Pullup/Pulldown

Resistors

JESD 17

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Ceramic (J)

DIPs

description

provide a TTL interface to a 5-V system environment.

The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input

is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright

© 1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVTH573 ...J OR W PACKAGE

SN74LVTH573 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

SN54LVTH573 . . . FK PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

LE

32 1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

2Q

3Q

4Q

5Q

6Q

3D

4D

5D

6D

7D

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.