FS714x

Then:

R1 (from CLKP and CLKN output to VDD) =

75 * 3.3 / 2.4 =

103 ohms

R2 (from CLKP and CLKN output to GND)

=

75 * 3.3 / (3.3 - 2.4) =

275 ohms

Rprgm (from VDD to IPRG pin)

=

26 * (3.3 * 75) / (2.4 - 1.6) / 3 =

2.68 Kohms

4.3 SYNC Circuitry

The FS7145 supports nearly instantaneous adjustment of the output CLK phase by the SYNC input. Either edge direction of SYNC

(positive-going or negative-going) is supported.

Example (positive-going SYNC selected): Upon the negative edge of SYNC input, a sequence begins to stop the CLK output. Upon the

positive edge, CLK resumes operation, synchronized to the phase of the SYNC input (plus a deterministic delay). This is performed by

control of the device post-divider. Phase resolution equal to ½ of the VCO period can be achieved (approximately down to 2ns).

5.0 I

This device is a read/write slave device meeting all Philips I

controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP

conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master

device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving

data as the receiver.

I

5.1 Bus Conditions

Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable

whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START

or STOP condition. The following bus conditions are defined by the I

5.1.1. Not Busy

Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.

5.1.2. START Data Transfer

A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be

preceded by a START condition.

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