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SN74LVTH573 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVTH573 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 7 page SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687E – MAY 1997 – REVISED APRIL 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH573 is characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74LVTH573 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L HL L L LX Q0 H X X Z logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. OE 1D 2 1D 3 2D 4 3D 5 4D 6 5D C1 11 LE 1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12 7 6D 8 7D 9 8D EN 1 logic diagram (positive logic) OE To Seven Other Channels 1 11 2 19 LE 1D C1 1D 1Q |
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