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CAT5259YI-00 Datasheet(PDF) 2 Page - ON Semiconductor

Part # CAT5259YI-00
Description  Quad Digitally Programmable Potentiometers with 256 Taps and I짼C Interface
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT5259YI-00 Datasheet(HTML) 2 Page - ON Semiconductor

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CAT5259
Doc. No. MD-2000 Rev. I
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5259 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA: Serial Data
The CAT5259 bidirectional serial data pin is
used to transfer data into and out of the device.
The SDA pin is an open drain output and can
be wire-Ored with the other open drain or open
collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the
address
input
in
order
to
initiate
communication with the CAT5259.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent
to the terminal connections on a mechanical
potentiometer.
RW: Wiper
The four RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
WP
¯¯¯: Write Protect Input
The WP
¯¯¯ pin when tied low prevents non-volatile
writes to the device (change of wiper control
register is allowed) and when tied high or left
floating
normal
read/write
operations are
allowed. See Write Protection on page 6 for
more details.
DEVICE OPERATION
The CAT5259 is four resistor arrays integrated with a I²C serial interface logic, four 8-bit wiper control registers
and sixteen 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive
elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control
register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via
the I²C bus. Additional instructions allow data to be transferred between the wiper control registers and each
respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an
"increment/decrement" mode.
Pin
#
Name
Function
1
NC
No Connect
2
A0
Device Address, LSB
3
RW3
Wiper Terminal for Potentiometer 3
4
RH3
High Reference Terminal for Potentiometer 3
5
RL3
Low Reference Terminal for Potentiometer 3
6
NC
No Connect
7
VCC
Supply Voltage
8
RL0
Low Reference Terminal for Potentiometer 0
9
RH0
High Reference Terminal for Potentiometer 0
10
RW0
Wiper Terminal for Potentiometer 0
11
A2
Device Address
12
WP
¯¯¯
Write Protection
13
SDA
Serial Data Input/Output
14
A1
Device Address
15
RL1
Low Reference Terminal for Potentiometer 1
16
RH1
High Reference Terminal for Potentiometer 1
17
RW1
Wiper Terminal for Potentiometer 1
18
GND
Ground
19
NC
No Connect
20
RW2
Wiper Terminal for Potentiometer 2
21
RH2
High Reference Terminal for Potentiometer 2
22
RL2
Low Reference Terminal for Potentiometer 2
23
SCL
Bus Serial Clock
24
A3
Device Address


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