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SN74LVTH182652A Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVTH182652A Datasheet(HTML) 2 Page - Texas Instruments |
2 / 10 page SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS312C – MARCH 1994 – REVISED JUNE 1997 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B-port outputs of ’LVTH182652A, which are designed to source or sink up to 12 mA, include equivalent 25- Ω series resistors to reduce overshoot and undershoot. The SN54LVTH18652A and SN54LVTH182652A are characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74LVTH18652A and SN74LVTH182652A are characterized for operation from –40 °C to 85°C. 1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6 SN54LVTH18652A, SN54LVTH182652A . . . HV PACKAGE (TOP VIEW) 28 29 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 32 33 34 87 6 5 4 93 1 68 67 2 35 36 37 38 39 66 65 27 64 63 62 61 40 41 42 43 NC – No internal connection |
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