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SN54LVTH18514 Datasheet(PDF) 5 Page - Texas Instruments |
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SN54LVTH18514 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 34 page SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Std 1149.1-1990. Test instructions, test data, and test control signals are passed along this serial-test bus. The TAP controller monitors two signals from the test bus: TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully one-half of the TCK cycle. The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationships of the test bus, the TAP controller, and the test registers. As shown, the device contains an 8-bit instruction register and four test data registers: a 48-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register. Test-Logic-Reset Run-Test/Idle Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Update-DR TMS = L TMS = L TMS = H TMS = L TMS = H TMS = H TMS = L TMS = H TMS = L TMS = L TMS = H TMS = L Exit2-DR Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Update-IR TMS = L TMS = L TMS = H TMS = L TMS = H TMS = H TMS = L TMS = H TMS = L Exit2-IR TMS = L TMS = H TMS = H TMS = H TMS = L TMS = H TMS = L TMS = H TMS = H TMS = H TMS = L Figure 1. TAP-Controller State Diagram |
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