SN54LVT8996JT datasheet(10/44 Pages) TI

Part #	SN54LVT8996JT

Description	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS

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SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

10

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short address

In all cases, receipt of an address shorter than ten bits produces protocol result HARD ERROR and the ASP

assumes OFF status.

connect control

The connect-control block monitors the primary TAP state to enable receipt/acknowledge of shadow protocols

in appropriate states (namely, the stable, non-Shift TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-DR,

and Pause-IR). Upon receipt of a valid shadow protocol, this block performs the address matching required to

compute the shadow-protocol result.

TAP-state monitor

The TAP-state monitor is a synchronous finite-state machine that monitors the primary TAP state. The state

diagram is shown in Figure 5 and mirrors that specified by IEEE Std 1149.1-1990. The TAP-state monitor

proceeds through its states based on the level of PTMS at the rising edge of PTCK. Each state is described both

in terms of its significance for ASP devices and for connected IEEE Std 1149.1-compliant devices (called

targets). However, the monitor state (primary TAP) can be different from that of disconnected scan chains

(secondary TAP).

Test-Logic-Reset

Run-Test /Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = L

Exit2-IR

PTMS = L

PTMS = H

PTMS = L

PTMS =H

PTMS = H

PTMS = L

PTMS = H

PTMS = L

Figure 5. TAP-Monitor State Diagram

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SN54LVT8996JT Datasheet(PDF) 10 Page - Texas Instruments

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