SN54LVCH245A, SN74LVCH245A

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCES008F – JULY 1995 - REVISED JUNE 1998

1

POST OFFICE BOX 655303

CMOS) Submicron Process

Live Insertion

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

All Ports (5-V Input/Output Voltage With

Need for External Pullup/Pulldown

Resistors

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Flat (W) Package,

Ceramic Chip Carriers (FK), and DIPs (J)

description

These devices are designed for asynchronous communication between data buses. These devices transmit

data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are

effectively isolated.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54LVCH245A is characterized for operation over the full military temperature range of –55

°C to 125°C.

The SN74LVCH245A is characterized for operation from –40

°C to 85°C.

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVCH245A ...J OR W PACKAGE

SN74LVCH245A . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

DIR

A1

A2

A3

A4

A5

A6

A7

A8

GND

OE

B1

B2

B3

B4

B5

B6

B7

B8

SN54LVCH245A . . . FK PACKAGE

(TOP VIEW)

32

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

B1

B2

B3

B4

B5

A3

A4

A5

A6

A7

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.