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SN74LVC574ARGYR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC574ARGYR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 25 page SN54LVC574A, SN74LVC574A OCTAL EDGETRIGGERED DTYPE FLIPFLOPS WITH 3STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Operate From 1.65 V to 3.6 V D Inputs Accept Voltages to 5.5 V D Specified From −40°C to 85°C, −40 °C to 125°C, and −55°C to 125°C D Max tpd of 7 ns at 3.3 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C D Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54LVC574A ...J OR W PACKAGE SN74LVC574A . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN54LVC574A . . . FK PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2Q 3Q 4Q 5Q 6Q 3D 4D 5D 6D 7D SN74LVC574A . . . RGY PACKAGE (TOP VIEW) 120 10 11 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1D 2D 3D 4D 5D 6D 7D 8D description/ordering information The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Copyright 2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. |
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