SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

5

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

FROM

TO

SN54LV74

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V ± 0.5 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

fmax

70

100

60

90

50

MHz

tpd

PRE or CLR

QorQ

11

19

18

27

34

ns

tpd

CLK

Q or Q

10

17

17

26

28

ns

(unless otherwise noted) (see Figure 1)

FROM

TO

SN74LV74

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V ± 0.5 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

fmax

70

100

60

90

50

MHz

tpd

PRE or CLR

QorQ

11

19

18

27

34

ns

tpd

CLK

Q or Q

10

17

17

26

28

ns

PARAMETER

TEST CONDITIONS

VCC

TYP

UNIT

C d

Power dissipation capacitance per flip flop

CL =50 pF

f=10MHz

3.3 V

32

pF

Cpd

Power dissipation capacitance per flip-flop

CL = 50 pF,

f = 10 MHz

5 V

68

pF

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design phase of development. Characteristic data and other

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change or discontinue these products without notice.