KH561

DATA SHEET

REV. 1A January 2004

11

For the circuit of Figure 1, the equivalent input noise

voltage may be calculated using the data sheet spot

All terms cast as (nV/

Gain Accuracy (DC):

A classical op amp’s gain accuracy is principally set by

the accuracy of the external resistors. The KH561

also depends on the internal characteristics of the

forward current gain and inverting input impedance. The

Thevinin model of Figure 5 are the most direct way of

assessing the absolute gain accuracy. Note that internal

temperature drifts will decrease the absolute gain

slightly as the part warms up. Also note that the para-

meter tolerances affect both the signal gain and output

impedance. The gain tolerance to the load must include

both of these effects as well as any variation in the load.

The impact of each parameter shown in the performance

Increasing current gain G

Applications Suggestions

Driving a Capacitive Load:

The KH561 is particularly suitable for driving a capacitive

load. Unlike a classical op amp (with an inductive output

impedance), the KH561’s output impedance, while

starting out real at the programmed value, goes some-

what capacitive at higher frequencies. This yields a very

stable performance driving a capacitive load. The over-

all response is limited by the (1/RC) bandwidth set by the

KH561’s output impedance and the load capacitance. It

data sheet plots.

Note from distortion plots into a

capacitive load that the KH561 achieves better than

through 30MHz.

Improving the Output Impedance Match

Using the loop gain to provide a non-zero output

impedance provides a very good impedance match at

low frequencies. As shown on the Output Return Loss

plot, however, this match degrades at higher frequencies.

Adding a small external resistor in series with the output,

match over frequency. Figure 9 shows this approach.

Figure 9: Improving Output Impedance

Match vs. Frequency

with the desired output match.

As discussed in the

limiting the internal power under an output shorted

condition.

Interpreting the Slew Rate:

The slew rate shown in the data sheet applies to the volt-

age swing at the load for the circuit of Figure 1. Twice this

value would be required of a low output impedance

amplifier using an external matching resistor to achieve

the same slew rate at the load.

Layout Suggestions:

The fastest fine scale pulse response settling requires

careful attention to the power supply decoupling.

Generally, the larger electrolytic capacitor ground

connections should be as near the load ground (or cable

shield connection) as is reasonable, while the higher

frequency ceramic de-coupling caps should be as near

the KH561’s supply pins as possible to a low inductance

ground plane.

Evaluation Boards:

An evaluation board (showing a good high frequency lay-

out) for the KH561 is available.

This board may be

ordered as part #730019.

Thermal Analysis and Protection

A thermal analysis of a chip and wire hybrid is

directed

at

determining

the

maximum

junction

temperature of all the internal transistors. From the total

internal power dissipation, a case temperature may be

developed using the ambient temperature and the case

to ambient thermal impedance.

Then, each of the

dominant power dissipating paths are considered to

determine which has the maximum rise above case

temperature.

The thermal model and analysis steps are shown below.

As is typical, the model is cast as an electrical model

where the temperatures are voltages, the power dissipa-

tors are current sources, and the thermal impedances

are resistances. Refer to the summary design equations

and Figure 1 for a description of terms.

e

2.1

.07

.632

1.22

.759

.089

2.62nV/ Hz

n

22

2

2

2

2

=

=

KH561

+

-

With:

A