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CDK3400CTQ48 Datasheet(PDF) 10 Page - Cadeka Microcircuits LLC. |
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CDK3400CTQ48 Datasheet(HTML) 10 Page - Cadeka Microcircuits LLC. |
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10 / 11 page  ©2008 CADEKA Microcircuits LLC www.cadeka.com 10 Data Sheet R9-0 G9-0 B9-0 +5V 0.1µF 10µF VDD GND CDK3400/3401 Triple 10-bit D/A Converter CLK SYNC BLANK RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK COMP VREF RREF +5V 0.1µF 0.1µF 560Ω 3.3kΩ (not required without external reference) LM185-1.2 (Optional) IOR IOG IOB 75Ω 75Ω 75Ω 75Ω 75Ω 75Ω Zo = 75Ω Red Green w/Sync Blue Zo = 75Ω Zo = 75Ω Figure 9. Typical Interface Circuit Diagram Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The CDK3400/3401 should be located near the board edge, close to the analog out-put connectors. 2. Power plane for the CDK3400/3401 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the CDK3400/3401 is the same as that of the system’s digital circuitry, power to the CDK3400/3401 should be decoupled with 0.1µF and 0.01µF capacitors and iso-lated with a ferrite bead. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the CDK3400/3401, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the CDK3400/3401 and its related analog circuitry can have an adverse effect on performance. 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Evaluation boards are available (CEB3400 and CEB3401), contact CADEKA for more information. Related Products n CDK3402/3403 Triple 8-bit 100/150MSPS DACs n CDK3404 Triple 8-bit 180MSPS DAC Applications Dicussion Figure 9 below illustrates a typical CDK3400/3401 inter- face circuit. In this example, an optional 1.2V bandgap reference is connected to the VREF output, overriding the internal voltage reference source. Grounding It is important that the CDK3400/3401 power supply is well- regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The CDK3400/3401 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. |
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