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SN74GTL16612DGG Datasheet(PDF) 2 Page - Texas Instruments |
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SN74GTL16612DGG Datasheet(HTML) 2 Page - Texas Instruments |
2 / 13 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED JULY 2005 Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74GTL16612DL SSOP – DL GTL16612 –40 °C to 85°C Tape and reel SN74GTL16612DLR TSSOP – DGG Tape and reel SN74GTL16612DGGR GTL16612 –55 °C to 125°C CFP – WD Tube SNJ54GTL16612WD SNJ54GTL16612WD (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE(1) INPUTS OUTPUT MODE B CEAB OEAB LEAB CLKAB A X H X X X Z Isolation L L L H X B0(2) Latched storage of A data L L L L X B0(3) X L H X L L Transparent X L H X H H L L L ↑ L L Clocked storage of A data L L L ↑ H H H L L X X B0(3) Clock inhibit (1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established 2 |
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