SN54F299, SN74F299

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

WITH 3-STATE OUTPUTS

SDFS071A – MARCH 1987 – REVISED OCTOBER 1993

Copyright

2–1

POST OFFICE BOX 655303

Hold (Store)

Shift Right

Shift Left

Load Data

Impedance

Stacked or Push-Down Registers

Buffer Storage

Accumulator Registers

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These 8-bit universal shift /storage registers

feature multiplexed I/O ports to achieve full 8-bit

data handling in a single 20-pin package. Two

function-select

(S0,

S1)

inputs

and

two

output-enable (OE1, OE2) inputs can be used to

choose the modes of operation listed in the

function table.

Synchronous parallel loading is accomplished by

taking both S0 and S1 high. This places the 3-state

outputs in a high-impedance state and permits

data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be

accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR) input is low.

Taking either OE1 or OE2 high disables the outputs but has no effect on clearing, shifting, or storage of data.

The SN54F299 is characterized for operation over the full military temperature range of – 55

°C to 125°C. The

SN74F299 is characterized for operation from 0

°C to 70°C.

SN54F299 ...J PACKAGE

SN74F299 . . . DW OR N PACKAGE

(TOP VIEW)

32

1 20 19

910 11 12 13

4

5

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7

8

18

17

16

15

14

SL

SN54F299 . . . FK PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

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11

S0

OE1

OE2

CLR

GND

S1

SL

CLK

SR

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.