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CT2-ML1PBTD33C Datasheet(PDF) 4 Page - JDS Uniphase Corporation

Part # CT2-ML1PBTD33C
Description  OC-48 SFP Transceiver (Multirate, 1310 nm, and 1550 nm)
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Manufacturer  JDSU [JDS Uniphase Corporation]
Direct Link  http://www.jdsu.com/index.html
Logo JDSU - JDS Uniphase Corporation

CT2-ML1PBTD33C Datasheet(HTML) 4 Page - JDS Uniphase Corporation

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4
OC-48 SFP TRANSCEIVER
CT2 Electrical Pad Layout
Transceiver Pin Descriptions
Pin
Description
TD
Un-clocked, multirate, differential serial bit stream (155 Mb/s to 2.7 Gb/s) used to drive the optical transmitter.
TDb
Internally AC coupled and terminated via internal 100
Ω differential impedence.
RD
Differential received electrical signal capable of detecting 155 Mb/s to 2.7 Gb/s bit patterns.
RDb
The differential pair is internally biased and AC coupled. This signal requires 100
Ω external differential termination.
Rate_select
Internally monitored and available for future use. Can be customized for specific applications.
TxDIS
Transmitter Disable Input. A logic HIGH on this input pin disables the transmitter's laser so that there is no optical
output. If left open the transmitter will be disabled.
LOS
Loss of Signal (Open Collector). A logic HIGH on this output indicates an incoming signal level that is less than
-25 dBm but no greater than -31 dBm for IR and SR configurations and less than -34 dBm but no greater than
-40 dBm for LR configurations. LOS shall deassert (logic LOW) when a 3 dB (maximum), 0.5 dB (minimum) hysteresis
is obtained.
Tx_fault
Transmitter fault (Open collector). A logic HIGH indicates that the transmitter is in a fault condition.
MOD_DEF(0)
MOD_DEF(0) is internally grounded to indicate the presence of the module. Must be pulled-up on host board with
10 K
Ω resistor.
MOD_DEF(1)
MOD_DEF(1) is the clock of the 2 wire interface for module monitoring.
MOD_DEF(2)
MOD_DEF(2) is the data line of the 2 wire interface for module monitoring.
VccR,VccT
Receiver, Transmitter power supply, respectively
VeeR, VeeT
Receiver, Transmitter ground, respectively. The chassis ground and circuit ground isolation is configurable.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VeeT
VeeT
VeeR
VeeR
VccR
VccT
TD-
TD+
RD+
RD-
VeeT
VeeR
VeeR
LOS
Tx Fault
Tx Disable
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
Top of Board
Bottom of Board (As Viewed
through Top of Board)


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