SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996

6

POST OFFICE BOX 655303

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.

The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller

proceeds through its states based on the level of TMS at the rising edge of TCK.

As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow

in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for

consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register may be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left

unconnected or if a board defect causes it to be open circuted.

For the ’BCT8240A, the instruction register is reset to the binary value 11111111, which selects the BYPASS

instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.

The test operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the

Capture-DR state, the selected-data register may capture a data value as specified by the current instruction.

Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the

Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the

first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic

level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.