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ADS-231 Datasheet(PDF) 4 Page - Murata Power Solutions Inc. |
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ADS-231 Datasheet(HTML) 4 Page - Murata Power Solutions Inc. |
4 / 12 page ADS-230/ADS-231 4 ® ® PIN DESCRIPTIONS AVS, DVS These are the analog and digital power supply input pins. They should all be connected to the same voltage source. Both AVS pins should be bypassed to AGND and the DVS pin to DGNDD. Bypass using a 0.1µF ceramic capacitor in parallel with a 10µF tantalum capacitor. AGND, DGNDC, DGNDD These are the analog and digital ground pins. All of the ground pins should be returned to the same potential and connected to a stable, noise-free system ground. AGND is the analog ground. DGNDC is the ground for the digital control lines. DGNDD is the digital ground for the output data bus. BIT 1 – BIT 12 These are the three-state data output pins. Output is enabled by RD, CS, and OE. CH1IN, CH2IN These are the analog input pins to the internal input multiplexer. MUX OUT This is the output of the internal multiplexer, ANALOG INPUT This is the direct input to the sampling A to D converter. SEL This is the multiplexer channel select pin. The input is selected based on the state of SEL when EOC transitions low. A low selects channel one and a high selects channel two. See Table 1. MD Connect to DGNDC TEST Connect to DVS. CS This is the Chip Select control input. When low, this pin enables the RD, S/H and OE inputs. This pin can be tied low. INT This is the Interrupt output pin. When using the Interrupt Interface Mode, this output goes low when a conversion is completed and indicates that the data is available in the output latches. This output is always high when RD is held low. Refer to the Timing Diagrams. EOC This is the End of Conversion output pin. EOC is low during a conversion. RD This is the Read control input pin. When RD and CS are low, the INT output is reset and, if EOC is high, data appears on the data bus. This pin can be tied low. OE This is the Output Enable control input pin. The data output pins are in the high impedance state when OE is low. Data appears when OE is high and CS and RD are both low. This pin can be tied high. S/H This is the Sample and Hold control input pin. When CS is low a new conversion is initiated by the falling edge of this input. PD This is the Power Down control input pin. This pin is held high for normal operation. When the input is low, the A to D converter goes into power standby mode. VR/16 Bypass this pin to AGND using a 0.1µF ceramic capacitor. VT, VB These are the positive (top) and negative (bottom) voltage reference force input pins, respectively. VTS, VBS These are the positive (top) and negative (bottom) voltage reference sense pins, respectively. |
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