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TDA9951 Datasheet(PDF) 9 Page - NXP Semiconductors |
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TDA9951 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 41 page TDA9951_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 7 August 2008 9 of 41 NXP Semiconductors TDA9951 CEC/I2C-bus translator Using ACKH and ACKL, each bit of ADDR[14:0] corresponds to a CEC logical address. CEC reserves ADDR[15] as a broadcast address. ADDR[14:0] is built-up from ACKH[6:0] and ACKL[7:0]. Communication between the TDA9951 and the host processor for the data registers is carried out using information frames transferred using the common data register subaddress range 07h to 19h. The common data registers CDR0 to CDR18 are described in detail in Section 8.5. 8.5 Data register protocol Before a frame is read or written, the host processor must set the REG_PTR field in the address pointer register to the base data register address. Message transfers can only start from the first data register at address 07h. They must not start from higher addresses because message transfer must be in complete sequences and not in fragments. Each frame consists of a byte count, service selector, followed by zero or more parameters as shown in Figure 3. Table 12. ACKL - CEC address ACK low register (address 05h) bit description Bit Symbol Access Value Description 7 to 0 reserved R/W for each bit: 0 messages are not acknowledged 1 messages are acknowledged and forwarded to the host Table 13. ADDR[14:0] definition Bit 7 6 5 4 3 2 1 0 ACKH - ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ACKL ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0] Table 14. CCONR - Common configuration register (address 06h) bit description Bit Symbol Access Value Description 7 to 5 not used R 000 not used; set to 000 4 ENABLE_ ERROR R/W controls how the TDA9951 notifies the host processor of errors: 0 default; errors are not reported using the TDA9951 Data.err service or common error register 1 errors reported using the TDA9951 Data.err service or common error register 3 INT_POL R/W sets the polarity of the INT output when it is active: 0 default; the I2C_INT output is active-LOW 1 the I2C_INT output is active-HIGH 2 to 0 RETRY[2:0] R/W these bits set the CEC retry count used by the TDA9951. The maximum value is 5; values greater than 5 give 5 retries: 0 to 4 valid retry count 5 default; maximum valid retry count 6 to 7 accepted as 5 retries |
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