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SN74ABT16843DGG Datasheet(PDF) 2 Page - Texas Instruments |
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SN74ABT16843DGG Datasheet(HTML) 2 Page - Texas Instruments |
2 / 8 page SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS223E – OCTOBER 1992 – REVISED MAY 1997 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16843 is characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74ABT16843 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each 9-bit latch) INPUTS OUTPUT PRE CLR OE LE D Q L X L X X H H LL X X L H HL HL L H HL H H H H HL L X Q0 X X H X X Z |
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