Altera Corporation

9

Excalibur Device Overview

In addition, there are either one or two blocks of dual-port SRAM in

the embedded stripe, depending on the device type. The outputs of

the dual-port memories can be registered. One of the ports gives

dedicated access to the PLD; the other port can be configured for

access by AHB masters or by the PLD. The width of the data port to

the PLD is configurable as ×8, ×16, or ×32 bits. For the larger devices,

the dual-port SRAM blocks can be combined to form a ×64-bit data-

width interface. This allows the designer to build deeper and wider

memories and multiplex the data outputs within the stripe.

External Memory Controllers

The Excalibur family provides two embedded memory controllers

that can be accessed by any of the bus masters: one for external

SDRAM, and a second for external flash memory or SRAM.

The SDRAM memory controller supports the following commonly-

available memory standards, without the addition of any logic:

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Single-data rate (SDR) 133-MHz data rates

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Double-data rate (DDR) 266-MHz data rates

An embedded stripe PLL supplies the appropriate timing to the

SDRAM memory controller subsystem. Users can program the

frequency to match the chosen memory components.

The EBI supports the interface to system ROM, allowing external

flash memory access and reprogramming. In addition, static RAM

and simple peripherals can be connected to this interface externally.

Embedded Peripherals

A single 16-Kbyte memory region in the embedded stripe contains

configuration and control registers, plus status and control registers

for the embedded peripherals. The region contains the following

modules:

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Configuration Registers

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Embedded Stripe PLLs

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UART

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Timer

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Watchdog timer

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General Purpose I/O Port

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Interrupt controller