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SN28837 Datasheet(PDF) 3 Page - Texas Instruments

Part No. SN28837
Description  1/2-INCH PAL TIMER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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The levels on these three terminals determine which of the five antiblooming modes is selected:
Mode
ABS2
ABS1
ABS0
Operation
0
NC
L
L
No ABG pulses
1
NC
H
L
2-MHz burst of ABG pulses
2
NC
L
H
1-MHz burst of ABG pulses
3
H
H
H
1-MHz continuous ABG pulses
4
L
H
H
2-MHz continuous ABG pulses
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ABIN
38
O
Antiblooming in
ABS0
21
I
ABS1
22
I
ABS2
23
I
Mode 1 is used for normal operation.
BCP1
1
O
Optical black clamp
BCP2
2
O
Optical black clamp
BF
7
O
Burst flag
CBLK
6
O
Composite blank
CLK
50
O
3.34-MHz clock (factory-test point)
CLK13M
47
O
13-MHz clock (connect to SN28838 color-subcarrier generator for color operation)
CP1
3
O
Clamp 1 (signal processing)
CP2
4
O
Clamp 2 (signal processing)
CSYNC
5
O
Composite sync
E/L
19
I
Delay select for S1, S2, S3. When E/L is high, the three serial-transfer pulses occur early relative to the
sample-and-hold pulses SH1, SH2, and SH3. When E/L is low, the three serial-transfer pulses occur late
relative to the sample-and-hold pulses.
FI
13
O
Field index
GND
41, 60
Ground
GP
27
I
Exposure control: GP gates the PS and PI outputs (see the description of GPS)
GPS
26
I
When GPS is high, the timer operates in the normal-integration-time mode (tint = 20 ms) and VD is
connected internally to GP. To operate the imager in the variable-integration-time mode, GPS must be
held low and a user-defined logic circuit must be inserted between VD and GP to vary the integration time
(see Figure 1).
GT
37
O
TMS3473B parallel-driver MIDSEL input switch
GT1/SH3
56
O
GT1/SH3 is a logic signal for both Y gate 1 of the TL1051 video preprocessor and sample-and-hold
channel 3 of the TL1593 3-channel sample-and-hold circuit.
GT2
57
O
Y gate 2 for the TL1051 video preprocessor
GT3/SH2
53
O
GT3/SH2 is a logic signal for both Y gate 3 of the TL1051 video preprocessor and sample-and-hold
channel 2 of the TL1593 3-channel sample-and-hold circuit.
HCR
59
I
Horizontal-counter reset
HGATE
11
O
Decoded H count signal. HGATE is a test point and is not used in normal operation.
HIGH
25
I
Not used (tie high)
IDP
10
O
ID pulse (for SECAM operation)
LSW
48
O
Line switch (connect to SN28838 for color operation)
NC
15, 30,
35, 46,
52, 54, 55
No connect
PD
49
O
Power down. A low-logic level on PD causes the device to enter a low power-consumption mode.
PI
39
O
Parallel-image-area gate clock
PS
36
O
Parallel-storage-area gate clock
SB
29
I
Standby-mode select. When SB is high, normal operation is selected; when SB is low, the power-down
mode is selected.
SCBLK
9
O
Subcarrier blank (for SECAM applications)




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