EN25D16-100VI datasheet(9/37 Pages) EON

Part #	EN25D16-100VI

Description	16 Megabit Serial Flash Memory

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Manufacturer	EON [Eon Silicon Solution Inc.]

Direct Link	http://www.essi.com.tw

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This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

9

EN25D16

Rev. B, Issue Date: 2008/06/23

In addition to the low power consumption feature, the Deep Power-down mode offers extra

software protection from inadvertent Write, Program and Erase instructions, as all instructions

are ignored except one particular instruction (the Release from Deep Power-down instruction).

TABLE 3. Protected Area Sizes Sector Organization

Status Register

Content

Memory Content

BP2

Bit

BP1

Bit

BP0

Bit

Protect Blocks

Addresses

Density(KB)

Portion

1

All

000000h-1FFFFFh

2048KB

All

1

0

All

000000h-1FFFFFh

2048KB

All

1

0

1

16 to 31

100000h-1FFFFFh

1024KB

Upper 1/2

1

0

24 to 31

180000h-1FFFFFh

512KB

Upper 1/4

0

1

28 to 31

1C0000h-1FFFFFh

256KB

Upper 1/8

0

1

0

30 to 31

1E0000h-1FFFFFh

128KB

Upper 1/16

0

1

31

1F0000h-1FFFFFh

64KB

Upper 1/32

0

None

Hold Function

The Hold (HOLD) signal is used to pause any serial communications with the device without reset-

ting the clocking sequence. However, taking this signal Low does not terminate any Write Status

Register, Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold

condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial

Clock (CLK) being Low (as shown in Figure 4.).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides

with Serial Clock (CLK) being Low.

If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts af-

ter Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock

(CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in

Figure 4.).

During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)

and Serial Clock (CLK) are Don’t Care.

Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of

the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the

moment of entering the Hold condition.

If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is necessary to

drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from

going back to the Hold condition.

Figure 4. Hold Condition Waveform

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