EN29PL064-70CI datasheet(11/66 Pages) EON

Part #	EN29PL064-70CI

Description	64/32 Mbit (4/2 M x 16-Bit) CMOS 3.0 Volt- only,

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Manufacturer	EON [Eon Silicon Solution Inc.]

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11 / 66 page

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

11

EN29PL064/032

Rev. D, Issue Date: 2008/03/27

9. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated

through the internal command register. The command register itself does not occupy any

addressable memory location. The register is a latch used to store the commands, along with the

address and data information needed to execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

Table 9.1 lists the device bus operations, the inputs and control levels they require, and the resulting

output. The following subsections describe each of these operations in further detail.

Table 9.1

Device Bus Operations

Operation

CE#

OE#

WE#

RESET#

WP#/ACC

Addresses

(Amax–A0)

DQ15–

DQ0

Read

L

H

X

AIN

DOUT

Write

L

H

L

H

X (Note 2)

AIN

DIN

Standby

Vcc±0.3 V

X

Vcc ±0.3 V

X (Note 2)

X

High-Z

Output Disable

L

H

X

High-Z

Reset

X

L

X

High-Z

Temporary Sector

Unprotect (High Voltage)

X

VID

X

AIN

DIN

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 10.5–11.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector

Address, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes

1.

The sector protect and sector unprotect functions may also be implemented via programming equipment.

See High Voltage Sector Protection

2. WP#/ACC must be high when writing to upper two and lower two sectors.

9.1 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the OE# and appropriate CE# pins. CE#

is the power control. OE# is the output control and gates array data to the output pins. WE# should

remain at V

IH.

The internal state machine is set for reading array data upon device power-up, or after a hardware

reset. This ensures that no spurious alteration of the memory content occurs during the power

transition. No command is necessary in this mode to obtain array data. Standard microprocessor

read cycles that assert valid addresses on the device address inputs produce valid data on the

device data outputs. Each bank remains enabled for read access until the command register

contents are altered.

Refer to Table 21.3 for timing specifications and to Figure 20.3 for the timing diagram. I

CC1 in the

DC Characteristics table represents the active current specification for reading array data.

9.1.1 Random Read (Non-Page Read)

Address access time (t

ACC) is equal to the delay from stable addresses to valid output data.

The chip enable access time (t

CE) is the delay from the stable addresses and stable CE# to

valid data at the output inputs. The output enable access time is the delay from the falling

edge of the OE# to valid data at the output inputs (assuming the addresses have been stable

for at least t

ACC–tOE time).

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