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CY54FCT541TCERDIP Datasheet(PDF) 1 Page - Texas Instruments |
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CY54FCT541TCERDIP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page 8-Bit Buffers/Line Drivers CY54/74FCT540T CY54/74FCT541T SCCS029 - May 1994 - Revised March 2000 Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. Copyright © 2000, Texas Instruments Incorporated Features • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 4.1 ns max. (Com’l) FCT-A speed at 4.8 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • ESD > 2000V • Matched rise and fall times • Fully compatible with TTL input and output logic levels • Sink current 64 mA (Com’l), 48 mA (Mil) Source current 32 mA (Com’l), 12 mA (Mil) • Extended commercial range of −40˚C to +85˚C Functional Description The FCT540T inverting buffer/line driver and the FCT541T non-inverting buffer/line driver are designed to be employed as memory address drivers, clock drivers, and bus-oriented transmitters/receivers. The devices provide speed and drive capabilities equivalent to their fastest bipolar logic counterparts while reducing power dissipation. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices without external components. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Logic Block Diagram—FCT540T Pin Configurations 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 13 14 VCC 15 CERDIP/SOIC/QSOP Top View GND O0 D1 D2 D3 D4 D5 D6 D7 D0 O1 O2 O3 O4 O5 O6 O7 OEB OEA O0 D1 D2 D3 D4 D5 D6 D7 D0 O1 O2 O3 O4 O5 O6 O7 OEB OEA FCT540T 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 13 14 VCC 15 CERDIP/DIP/SOIC/QSOP Top View GND O0 D1 D2 D3 D4 D5 D6 D7 D0 O1 O2 O3 O4 O5 O6 O7 OEB OEA O0 D1 D2 D3 D4 D5 D6 D7 D0 O1 O2 O3 O4 O5 O6 O7 OEB OEA Logic Block Diagram—FCT541T FCT541T |
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