CDC857-2, CDC857-3

2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

6

POST OFFICE BOX 655303

timing requirements over recommended ranges or supply voltage and operating free–air

temperature

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

fC

Clock frequency

66

167

MHz

Input clock duty cycle

40%

60%

Stabilization time†

0.1

ms

† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed–frequency, fixed–phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay,

skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation

under SSC application.

switching characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tPLH‡

Low–to high level propagation delay time

(see Figure 5)

CLK mode/CLK to any output

1.5

3.5

6

ns

tPHL‡

High–to low level propagation delay time

(see Figure 5)

CLK mode/CLK to any output

1.5

3.5

6

ns

ten

Output enable time

CLK mode/G to any Y output

3

ns

tdis

Output disable time

CLK mode/G to any Y output

3

ns

t(jitt )

Jitter (peak to peak)

66 MHz

120

ps

t(jitter)

Jitter (peak-to–peak)

100/125/133/167 MHz

75

ps

t(jitt )

Jitter (cycle to cycle)

66 MHz

110

ps

t(jitter)

Jitter (cycle-to-cycle)

100/125/133/167 MHz

65

ps

t(phase error)

Phase error (see Figure 4)

All differential input and output termi-

–150

150

ps

tskew(0)

Output skew (see Figure 4)

All differential in ut and out ut termi-

nals are terminated with 120

Ω/

16 F

h

i Fi

2

100

ps

tskew(p)

Pulse skew

16 pF as shown in Figure 2

100

ps

Duty cycle§ (see Figure 6)

66 MHz to 100 MHz

49.5%

50.5%

Duty cycle§ (see Figure 6)

101 MHz to 167 MHz

49%

51%

tr, tf

Output rise and fall times (20% – 80%)

Load = 120

Ω/16 pF

650

800

950

ps

‡ Refers to transition of noninverting output.

§ While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty

cycle = twH/tc, were the cycle time (tc) decreases as the frequency goes up.