CDC857-2, CDC857-3

2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

Input voltage

All input pins

VCC = 2.3 V,

II = –18 mA

–1.2

V

VOH

High level output voltage

VCC = min to max, IOH= –1 mA

VCC–0.1

V

VOH

High-level output voltage

VCC = 2.3 V,

IOH = –12 mA

1.7

V

VOL

Low level output voltage

VCC = min to max, IOL = 1 mA

0.1

V

VOL

Low-level output voltage

VCC = 2.3 V,

IOL = 12 mA

0.6

V

IOH

High-level output current

VCC = 2.3 V,

VO = 1 V

–18

–32

mA

IOL

Low-level output current

VCC = 2.3 V,

VO = 1.2 V

26

35

mA

VO

Output voltage swing

For load condition see Figure 3

1.1

VCC–0.4

V

II

Input current

G

VCC = 2.7 V,

VI = 0 V to 2.7 V

µA

II

Input current

CLK, FBIN

VCC = 2.7 V,

VI = 0 V to 2.7 V

µA

IOZ

High impedance output current

VCC =2 7 V

VO =VCC or GND

µA

IOZ

High-impedance output current

VCC = 2.7 V,

VO = VCC or GND

µA

VOC

Output crossing point voltage‡

(VCC/2)–

0.1

VCC/2

(VCC/2)+

0.1

V

ICCZ

Supply current, disabled

AVCC and VCC = max,

G = L or no input CLK signal

500

800

µA

lCC

Supply current on VCC

(see Figure 7)

VCC = 2.7 V,

fO = 167 MHz,

All outputs switching 16 pF in 60

Ω

environment,

See Figure 3

235

300

mA

AICC

Supply current on

CDC857–2

AVCC = 2.7 V,

fO = 167 MHz

9

12

mA

AICC

Su

ly current on

AVCC

CDC857–3

AVCC = 3.6 V,

fO = 167 MHz

15

19

mA

CI

Input capacitance

VCC = 2.5 V,

VI = VCC or GND

2

pF

CO

Output capacitance

VCC = 2.5 V,VO = VCC or GND

3

pF

† All typical values are at respective nominal VCC.

‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input

signal voltage and VCP is the complementary input signal voltage (see Figure 3).