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6 Power Dissipation Capacitance (Notes 4, 5) CPD - 5 47 - - - pF HCT TYPES Propagation Delay, CP to Qn tPLH, tPHL CL = 50pF 4.5 - 36 45 54 ns CL = 15pF 5 15 - - - ns MR to Qn tPLH, tPHL CL = 50pF 4.5 - 38 46 57 ns CL = 15pF 5 16 - - - ns Output Transition Times tTLH, tTHL CL = 50pF 4.5 - 15 19 22 ns Input Capacitance CIN -- - - - - pF Maximum Clock Frequency fMAX CL = 15pF - 54 - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 49 10 10 10 pF NOTES: 5. CPD is used to determine the dynamic power consumption, per device. 6. PD =VCC 2 f i + ∑ (CL VCC 2 +f O) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Switching Specifications Input tr, tf = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITS TYP MAX MAX MAX Test Circuits and Waveforms FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS trCL tfCL GND VCC GND VCC 50% 90% 10% GND CLOCK INPUT DATA INPUT OUTPUT SET, RESET OR PRESET VCC 50% 50% 90% 10% 50% 90% tREM tPLH tSU(H) tTLH tTHL tH(L) tPHL IC CL 50pF tSU(L) tH(H) trCL tfCL GND 3V GND 3V 1.3V 2.7V 0.3V GND CLOCK INPUT DATA INPUT OUTPUT SET, RESET OR PRESET 3V 1.3V 1.3V 1.3V 90% 10% 1.3V 90% tREM tPLH tSU(H) tTLH tTHL tH(L) tPHL IC CL 50pF tSU(L) 1.3V tH(H) 1.3V CD74HC164, CD74HCT164 |
