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CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit Data Inputs Data Outputs CLR LOAD A B C D CLK ENP ENT RCO QA QB QC QD Async Clear Preset Count Inhibit 12 13 14 15 0 1 2 |
