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BQ4845S-A4 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ4845S-A4 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 22 page  Interrupts The bq4845 allows three individually selected interrupt events to generate an interrupt request on the INT pin. These three interrupt events are: s The periodic interrupt, programmable to occur once every 30.5 µs to 500ms s The alarm interrupt, programmable to occur once per second to once per month s The power-fail interrupt, which can be enabled to be asserted when the bq4845 detects a power failure The periodic, alarm, and power-fail interrupts are en- abled by an individual interrupt-enable bit in register C, the interrupts register. When an event occurs, its event flag bit in the flags register, register D, is set. If the cor- responding event enable bit is also set, then an interrupt request is generated. Reading the flags register clears all flag bits and makes INT high impedance. To reset the flag register, the bq4845 addresses must be held sta- ble at register D for at least 50ns to avoid inadvertent resets. Periodic Interrupt Bits RS3–RS0 in the interrupts register program the rate for the periodic interrupt. The user can interpret the interrupt in two ways: either by polling the flags register for PF assertion or by setting PIE so that INT goes active when the bq4845 sets the periodic flag. Reading the flags register resets the PF bit and returns INT to the high-impedance state. Table 4 shows the pe- riodic rates. Alarm Interrupt Registers 1, 3, 5, and 7 program the real-time clock alarm. During each update cycle, the bq4845 compares the date, hours, minutes, and seconds in the clock regis- ters with the corresponding alarm registers. If a match between all the corresponding bytes is found, the alarm flag AF in the flags register is set. If the alarm inter- rupt is enabled with AIE, an interrupt request is gener- ated on INT. The alarm condition is cleared by a read to the flags register. ALM1 – ALM0 in the alarm registers, mask each alarm compare byte. An alarm byte is masked by setting ALM1 (D7) and ALM0 (D6) to 1. Alarm byte masking can be used to select the frequency of the alarm interrupt, according to Table 5. The alarm interrupt can be made active while the bq4845 is in the battery-backup mode by setting ABE in the interrupts register. Normally, the INT pin goes high-impedance during battery backup. With ABE set, however, INT is driven low if an alarm condition occurs and the AIE bit is set. Because the AIE bit is reset dur- ing power-on reset, an alarm generated during power-on reset updates only the flags register. The user can read the flags register during boot-up to determine if an alarm was generated during power-on reset. Power-Fail Interrupt When VCC falls to the power-fail-detect point, the power-fail flag PWRF is set. If the power-fail interrupt enable bit (PWRIE) is also set, then INT is asserted low. The power-fail interrupt occurs tWPT before the bq4845 generates a reset and deselects. The PWRIE bit is cleared on power-up. Battery-Low Warning The bq4845 checks the battery on power-up. When the battery voltage is approximately 2.1V, the battery-valid flag BVF in the flags register is set to a 0 indicating that clock and RAM data may be invalid. 8 WD2 WD1 WD0 Normal Watchdog Time-out Period (t2,t3) Reset Time-out Period (t1) 0 0 0 1.5s 0.25s 0 0 1 23.4375ms 3.9063ms 0 1 0 46.875ms 7.8125ms 0 1 1 93.75ms 15.625ms 1 0 0 187.5ms 31.25ms 1 0 1 375ms 62.5ms 1 1 0 750ms 125ms 1 1 1 3s 0.5s Table 3. Watchdog Time-out Rates Aug. 1995 bq4845/bq4845Y |
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