Symbol

Parameter

-70/-70N

-85/-85N

-150/-150N

-200

Units

Conditions/Notes

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Write cycle time

70

-

85

-

150

-

200

-

ns

Chip enable to end

of write

55

-

75

-

100

-

150

-

ns

(1)

Address valid to end

of write

55

-

75

-

90

-

150

-

ns

(1)

Address setup time

0-

0-

0-

0

-

ns

Measured from

address valid to

beginning of write. (2)

Write pulse width

55

-

65

-

90

-

130

-

ns

Measured from

beginning of write to

end of write. (1)

Write recovery time

(write cycle 1)

5-

5-

5-

5

-

ns

Measured from WE

going high to end of

write cycle. (3)

Write recovery time

(write cycle 2)

15

-

15

-

15

-

15

-

ns

Measured from CE

going high to end of

write cycle. (3)

Data valid to end of

write

30

-

35

-

50

-

70

-

ns

Measured from first

low-to-high transition

of either CE or WE.

Data hold time

(write cycle 1)

0-

0-

0-

0

-

ns

Measured from WE

going high to end of

write cycle. (4)

Data hold time

(write cycle 2)

10

-

10

-

0

-

0

-

ns

Measured from CE

going high to end of

write cycle. (4)

Write enabled to

output in high Z

025

0

30

050

0

70

ns

I/O pins are in output

state. (5)

Output active from

end of write

5-

5-

5-

5

-

ns

I/O pins are in output

state. (5)

Notes:

1.

A write ends at the earlier transition of CE going high and WE going high.

2.

A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition

of CE going low and WE going low.

3.

4.

5.

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

Sept. 1996 D

bq4010/bq4010Y

6-6