bq4014/bq4014Y

Symbol

Parameter

-85

-120

Units

Conditions/Notes

Min.

Max.

Min.

Max.

Write cycle time

85

-

120

-

ns

Chip enable to end of write

75

-

100

-

ns

(1)

Address valid to end of write

75

-

100

-

ns

(1)

Address setup time

0

-

0

-

ns

Measured from address valid to

beginning of write. (2)

Write pulse width

65

-

85

-

ns

Measured from beginning of write to

end of write. (1)

Write recovery time

(write cycle 1)

5-

5-

ns

Measured from WE going high to end

of write cycle. (3)

Write recovery time

(write cycle 2)

15

-

15

-

ns

Measured from CE going high to end

of write cycle. (3)

Data valid to end of write

35

-

45

-

ns

Measured to first low-to-high

transition of either CE or WE.

Data hold time

(write cycle 1)

0-

0-

ns

Measured from WE going high to end

of write cycle. (4)

Data hold time

(write cycle 2)

10

-

10

-

ns

Measured from CE going high to end

of write cycle. (4)

Write enabled to output in

high Z

0

30

0

40

ns

I/O pins are in output state. (5)

Output active from end of

write

0

-

0

-

ns

I/O pins are in output state. (5)

Notes:

1.

A write ends at the earlier transition of CE going high and WE going high.

2.

A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition

of CE going low and WE going low.

3.

4.

5.

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

Sept. 1992

6