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BQ3285ESS- Datasheet(PDF) 8 Page - Texas Instruments |
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BQ3285ESS- Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 29 page  Power-Down/Power-Up Cycle The bq3285E and bq3285L power-up/power-down cycles are different. The bq3285L continuously monitors VCC for out-of- tolerance. During a power failure, when VCC falls below VPFD (2.53V typical), the bq3285L write-protects the clock and stor- age registers. The power source is switched to BC when VCC is less than VPFD and BC is greater than VPFD, or when VCC is less than VBC and VBC is less than VPFD. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VPFD, the power source is VCC. Write- protection continues for tCSR time after VCC rises above VPFD. The bq3285E continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below VPFD (4.17V typical), the bq3285E write-protects the clock and storage registers. When VCC is below VBC (3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VBC, the power source is VCC. Write-protection contin- ues for tCSR time after VCC rises above VPFD. Control/Status Registers The four control/status registers of the bq3285E/L are accessible regardless of the status of the update cycle (see Table 4). Register A Register A programs: n The frequency of the square-wave and the periodic event rate. n Oscillator operation. Register A provides: n Status of the update cycle. RS0–RS3 - Frequency Select These bits select one of the 13 frequencies for the SQW out- put and the periodic interrupt rate, as shown in Table 3. OS0–OS2 - Oscillator Control These three bits control the state of the oscillator and divider stages. A pattern of 010 enables RTC operation by turning on the oscillator and enabling the frequency divider. A pattern of 011 behaves as 010 but additionally transforms register C into a read/write register. This al- lows the 32.768kHz output on the square wave pin to be turned on. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When 010 is writ- ten, the RTC begins its first update after 500ms. UIP - Update Cycle Status This read-only bit is set prior to the update cycle. When UIP equals 1, an RTC update cycle may be in progress. UIP is cleared at the end of each update cycle. This bit is also cleared when the update transfer inhibit (UTI) bit in register B is 1. 8 Register A Bits 76543210 UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0 76543210 ---- RS3 RS2 RS1 RS0 76543210 - OS2 OS1 OS0 ---- 76543210 UIP ------- Reg. Loc. (Hex) Read Write Bit Name and State on Reset 7 (MSB) 6 5 4 3 2 1 0 (LSB) A 0A Yes Yes 1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 SQWE 0 DF na HF na DSE na C 0C Yes No 2 INTF 0 PF 0 AF 0 UF 0 - 0 32KE na - 0 - 0 D 0D Yes No VRT na -0-0- 0 - 0-0-0 - 0 Notes: na = not affected. 1. Except bit 7. 2. Read/write only when OSC2–OSC0 in register A is 011 (binary). Table 4. Control/Status Registers bq3285E/L |
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