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BQ2058CSN Datasheet(PDF) 2 Page - Texas Instruments |
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BQ2058CSN Datasheet(HTML) 2 Page - Texas Instruments |
2 / 14 page Pin Descriptions CHG Charge control output This push-pull output controls the charge path to the battery pack. Charging is al- lowed when low. CTL Pack disable input When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal opera- tion, the CTL pin is low. VSS Low potential input CSL Overcurrent sense low-side input This input is connected between the low-side discharge FET (or sense resistor) and BAT4N to enable overcurrent sensing in the battery pack’s ground path. BAT4N Battery 4 negative input This input is connected to the negative termi- nal of the cell designated BAT4 in Figure 2. BAT3N Battery 3 negative input This input is connected to the negative terminal of the cell designated BAT3 in Figure 2. BAT2N Battery 2 negative input This input is connected to the negative termi- nal of the cell designated BAT2 in Figure 2. BAT1N Battery 1 negative input This input is connected to the negative termi- nal of the cell designated BAT1 in Figure 2. This input is connected to BAT1P in a three- cell configuration. DSG Discharge control output This push-pull output controls the discharge path to the battery pack. Discharge is al- lowed when low. NSEL Number of cells input This input selects the number of series cells in the pack. NSEL should connect to VCC for four cells and to VSS for three cells. UVD Undervoltage delay input This input uses an external capacitor to VCC to set the undervoltage delay timing. OVD Overvoltage delay input This input uses an external capacitor to VCC to set the overvoltage delay timing. OCD Overcurrent delay input This input uses an external capacitor to VCC to set the overcurrent delay timing. VCC High potential input CSH Overcurrent sense high-side input This input is connected between the high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack’s positive supply path. BAT1P Battery 1 positive input This input is connected to the positive terminal of the cell designated BAT1 in Figure 2. 2 bq2058 Number of Cells Configuration Pins Battery Pins 3 cells BAT1N tied to BAT1P NSEL = VSS BAT1N – Positive terminal of first cell BAT2N – Negative terminal of first cell BAT3N – Negative terminal of second cell BAT4N – Negative terminal of third cell 4 cells NSEL = VCC BAT1P – Positive terminal of first cell BAT1N – Negative terminal of first cell BAT2N – Negative terminal of second cell BAT3N – Negative terminal of third cell BAT4N – Negative terminal of fourth cell Table 1. Pin Configuration for 3- and 4-Series Cells |
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