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PPECL2-5 Datasheet(PDF) 1 Page - Rhombus Industries Inc.

Part # PPECL2-5
Description  100K ECL Logic 4-Bit Programmable Delay Modules
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Manufacturer  RHOMBUS-IND [Rhombus Industries Inc.]
Direct Link  http://www.rhombus-ind.com
Logo RHOMBUS-IND - Rhombus Industries Inc.

PPECL2-5 Datasheet(HTML) 1 Page - Rhombus Industries Inc.

  PPECL2-5 Datasheet HTML 1Page - Rhombus Industries Inc.  
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15801 Chemical Lane, Huntington Beach, CA 92649-1595
Phone: (714) 898-0960 • FAX: (714) 896-0971
www.rhombus-ind.com • email: sales@rhombus-ind.com
Rhombus
Industries Inc.
For other values & Custom Designs, contact factory.
Specifications subject to change without notice.
PPECL2 9901
1.300
MAX
(33.02)
MAX
.030
(0.76)
TYP.
.050
(1.27)
TYP.
.350
(8.89)
.400
(10.16)
.520
(13.21)
MAX.
.010
(0.25)
TYP.
.100
(2.54)
TYP.
.020
(0.51)
TYP.
.120
(3.05)
MIN.
24-Pin Package with Unused Pins Removed per Schematic. Dimensions inches (mm)
P2
7
P3
21
OUT
100K ECL
16 to 1 MUX
V
6
8
P4
20
17
18
19
Output
Buffer
22
P1
Passive
Delay
Network
IN
CC
V
CCA
V
EE
Internal Termination
100 Ohm Thevenin to -2V
Schematic Diagram
100K ECL Logic 4-Bit Programmable Delay Modules
ELECTRICAL SPECIFICATIONS @ 25°C
Inherent Delay Time (Step 0) ..................... 2.00 ns + 0.50 ns
Delay Per Programming Step ................................ See Table
Maximum Programming Delay ................. 2 ns + (15 x Step)
Output Rise Time (20% to 80%) ........................ 2.00 ns Max.
4-Bit Prog.
100K ECL
Part Number
Delay per
Step (ns)
Error ref.
to 0000
(ns)
Initial Delay
(ns)
Output Delay (ns) Referenced to "0000" per Program Setting (P4*P3*P2*P1)
0000
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
PPECL2P25
0.25 ± .12
± 0.50
2.0 ± 0.5
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
PPECL2P50
0.50 ± .25
± 0.50
2.0 ± 0.5
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
6.50
7.00
7.50
PPECL2P75
0.75 ± .35
± 1.0
2.0 ± 0.5
0.00
0.75
1.50
2.25
3.00
3.75
4.50
5.25
6.00
6.75
7.50
8.25
9.00
9.75 10.50 11.25
PPECL2-1
1.00 ± .50
± 1.0
2.0 ± 0.5
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00 10.00 11.00 12.00 13.00 14.00 15.00
PPECL2-1.25
1.25 ± .60
± 1.0
2.0 ± 0.5
0.00
1.25
2.50
3.75
5.00
6.25
7.50
8.75 10.00 11.25 12.50 13.75 15.00 16.25 17.50 18.75
PPECL2-1.5
1.50 ± .60
± 1.0
2.0 ± 0.5
0.00
1.50
3.00
4.50
6.00
7.50
9.00 10.50 12.00 13.50 15.00 16.50 18.00 19.50 21.00 22.50
PPECL2-2
2.00 ± .70
± 1.5
2.0 ± 0.5
0.00
2.00
4.00
6.00
8.00 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00
PPECL2-2.5
2.50 ± .70
± 1.5
2.0 ± 0.5
0.00
2.50
5.00
7.50 10.00 12.50 15.00 17.50 20.00 22.50 25.00 27.50 30.00 32.50 35.00 37.50
PPECL2-3
3.00 ± .70
± 1.5
2.0 ± 0.5
0.00
3.00
6.00
9.00 12.00 15.00 18.00 21.00 24.00 27.00 30.00 33.00 36.00 39.00 42.00 45.00
PPECL2-4
4.00 ± .80
± 3.0
2.0 ± 0.5
0.00
4.00
8.00 12.00 16.00 20.00 24.00 28.00 32.00 36.00 40.00 44.00 48.00 52.00 56.00 60.00
PPECL2-5
5.00 ± 1.0
± 3.0
2.0 ± 0.5
0.00
5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00
OPERATING SPECIFICATIONS
V
EE , Supply Voltage .......................................
-4.2 to -5.7VDC
I
EE , Supply Current
................................................. 95 mA typ.
Logic "1" Input:
V
IH ......................................... -1.165V min.
I
IH ........................................... 300 µA max.
Logic "0" Input:
V
IL ......................................... -1.475V max.
I
IL ............................................. 0.5 µA min.
V
OH Logic "1" Voltage Out .................................... -1.025 V min.
V
OL Logic "0" Voltage Out ..................................... -1.620V max.
Storage Temperature Range ............................. -55o to +125oC
Operating Temperature Range ................................ 0o to +85oC
** Pin 22, Input is internally connected to 16 standard 100K inputs and
is internally terminated by Thevenin equivalent of 100 Ohms to -2V.
TEST CONDITIONS
V
EE Supply Voltage
................................................. -4.50 VDC
Input Pulse Rise Time ............................................. 2.0ns max.
Input Pulse Frequency .................................................. 10 MHz
Input Pulse Duty Cycle ...................................................... 50%
1. Measurements made at 25 oC
2. Output Terminated through 50 ohms to -2.00 VDC.
3. Delays measured at 50% level of leading edge.


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