11

P/N: PM1231

REV. 1.8, JUL. 17, 2008

MX25L4005A

(4) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out

on SO (see Figure. 14)

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status

register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress.

When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch.

When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write

status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept

program/erase/write status register instruction.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined

in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the

Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits

define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip

Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#)

pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal

is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for

execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SRWD

BP2

BP1

BP0

WEL

WIP

Status

0

0

the level of the level of the level of

(write enable

(write in progress

Register Write

protected

protected

protected

latch)

bit)

Protect

block

block

block

1= status

(note 1)

(note 1)

(note 1)

1=write enable 1=write operation

register write

0=not write

0=not in write

disable

enable

operation

Note: 1. See the table "Protected Area Sizes".

2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed

as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.