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L9D125G80BG4M8 Datasheet(PDF) 9 Page - LOGIC Devices Incorporated |
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L9D125G80BG4M8 Datasheet(HTML) 9 Page - LOGIC Devices Incorporated |
9 / 45 page LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D125G80BG4-C 9 2.5 Gb, DDR - SDRAM Integrated Module (IMOD) PreLIMINArY INforMAtIoN L9D125G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION Figure 1 - moDe register DeFinition Burst Type Sequential Interleaved CAS Latency Reserved Reserved 2 Reserved Reserved 2.5 Reserved Burst length CAS Latency BT 0 A9 A7 A6 A5 A4 A3 0 A 1 A 2 A 8 A Mode register (Mx) Address bus 9 7 6 5 4 3 8 2 1 0 M3 0 1 M4 0 1 0 1 0 1 0 1 M5 0 0 1 1 0 0 1 1 M6 0 0 0 0 1 1 1 1 Operating mode . . . An BA0 BA1 . . . n1 0 Operating Mode Normal operation Normal operation/reset DLL All other states reserved M8 0 1 – M9 0 0 – . . . 0 0 – Mn 0 0 – M7 0 0 – M6–M0 Valid Valid – Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved M0 0 1 0 1 0 1 0 1 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1 0 1 0 1 Mode Register Definition Base mode register Extended mode register Reserved Reserved Mn + 2 0 0 1 1 Note: 1. n is the most significant row address bit Mn + 1 n + 2 n + 1 3 |
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