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LTC4253A-ADJ Datasheet(PDF) 8 Page - Linear Technology |
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LTC4253A-ADJ Datasheet(HTML) 8 Page - Linear Technology |
8 / 32 page LTC4253A-ADJ 8 4253a-adjf EN2 (Pin 1/Pin 18): Power Good Status Output Two Enable. This is a TTL compatible input that is used to control PWRGD2 and PWRGD3 outputs. When EN2 is driven low, both PWRGD2 and PWRGD3 will go high. When EN2 is driven high, PWRGD2 will go low provided PWRGD1 has been active for more than one power good sequence delay (tSQT) provided by the sequencing timer. EN2 can be used to control the power good sequence. This pin is internally pulled low by a 120 µA current source. PWRGD2 (Pin 2/Pin 19): Power Good Status Output Two. Power good sequence starts with DRAIN going below 2.39V and GATE is within 2.8V on VIN. PWRGD2 will latch active low after EN2 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD1 goes low, whichever comes later. PWRGD2 is reset by PWRGD1 going high or EN2 going low. This pin is internally pulled high by a 50 µA current source. PWRGD1 (Pin 3/Pin 20): Power Good Status Output One. At start-up, PWRGD1 latches active low one tSQT after both DRAIN is below 2.39V and GATE is within 2.8V of VIN. PWRGD1 status is reset by undervoltage, VIN (UVLO), RESET going high or circuit breaker fault time-out. This pin is internally pulled high by a 50 µA current source. VIN (Pin 4/Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V above VEE. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9V), overriding undervoltage and overvoltage events. If there is no undervoltage, no overvoltage and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating GATE ramp up. If VIN drops below approximately 8.5V, GATE pulls low immediately. RESET (Pin 5/Pin 2): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs high. The RESET pin has an internal glitch filter that rejects any pulse < 20 µs. After the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in Interlock Conditions in the Operation section. SS (Pin 6/Pin 3): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20X attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the beginning of the start-up cycle, the SS capacitor (CSS) is ramped by a 28 µA current source. The GATE pin is held low until SS exceeds 20 • VOS = 0.2V. SS is internally shunted by a 50k RSS which limits the SS pin voltage to 1.4V. This corresponds to an analog current limit SENSE voltage of 60mV. SEL (Pin 7/Pin 4): Soft-Start Mode Select. This is an asynchronous TTL compatible input. SEL has an internal pull-up of 20 µA that will pull it high if it is floated. SEL selects between two modes of SS ramp-up (see Applica- tions Information, Soft-Start section). SENSE (Pin 8/Pin 5): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (200 µA+8•IDRN) TIMER pull-up current. If SENSE exceeds VACL (60mV), the analog current-limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a cata- strophic short-circuit, SENSE may overshoot VACL. If SENSE reaches VFCL (200mV), the fast current-limit com- parator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. VEE (Pins 9, 10/Pin 7): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 11/Pin 8): N-channel MOSFET Gate Drive Output. This pin is pulled high by a 50 µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), undervoltage, overvoltage, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high. GATE is actively servoed to control the fault current as measured at SENSE. Compensation capacitor, CC, at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, then the GATE ramps up after an overvoltage event or PI FU CTIO S (SSOP/QFN) |
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