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LTC4151CDD-TRPBF Datasheet(PDF) 11 Page - Linear Technology |
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LTC4151CDD-TRPBF Datasheet(HTML) 11 Page - Linear Technology |
11 / 16 page LTC4151/LTC4151-1 11 41511fa APPLICATIONS INFORMATION Table 1. LTC4151/LTC4151-1 Device Addressing* DESCRIPTION HEX DEVICE ADDRESS BINARY DEVICE ADDRESS LTC4151/LTC4151-1 ADDRESS PINS h a6a5a4a3a2a1a0 R/W ADR1 ADR0 Mass Write CC 11001100 X X 0 CE 1100111 X H L 1 D0 1101000 X NC H 2 D2 1101001 X H H 3 D4 1101010 X NC NC 4 D6 1101011 X NC L 5 D8 1101100 X L H 6 DA 1101101 X H NC 7 DC 1101110 X L NC 8 DE 1101111 X L L *H = Tie High; L = Tie to GND; NC = Open; X = Don’t Care Acknowledge The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. The LTC4151/LTC4151-1 pull the SDA line low on the 9th clock cycle to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master can abort the transmission by generating a Stop condition. When the master is receiving data from the slave, the master must pull down the SDA line during the clock pulse to indicate receipt of a data byte, and that another byte is to be read. After the last byte has been received the master will leave the SDA line high (not acknowledge) and issue a Stop condition to terminate the transmission. Write Protocol The master begins a write operation with a Start condi- tion followed by the seven bit slave address and the R/W bit set to zero. After the addressed LTC4151/LTC4151-1 acknowledge the address byte, the master then sends a command byte which indicates which internal register the master wishes to write. The LTC4151/LTC4151-1 acknowledge this and then latches the lower three bits of the command byte into its internal register address pointer. The master then delivers the data byte and the LTC4151 or LTC4151-1 acknowledges once more and latches the data into its internal register. If the master continues sending a second byte or more data bytes, as in a Write Word or Write Page command, the second byte or more data bytes will be acknowledged by the LTC4151/LTC4151-1, the internal register address pointer will increment automatically, and each byte of data will be latched into an internal register corresponding to the address pointer. The write operation terminates and the register address pointer resets to 00h when the master sends a Stop condition. Read Protocol The master begins a read operation with a Start condition followed by the seven bit slave address and the R/W bit set to zero.AftertheaddressedLTC4151/LTC4151-1acknowledge the address byte, the master then sends a command byte that indicates which internal register the master wishes to read. The LTC4151/LTC4151-1 acknowledge this and then latches the lower three bits of the command byte into its internal register address pointer. The master then sends a repeated Start condition followed by the same seven bit address with the R/W bit now set to one. The LTC4151/ LTC4151-1 acknowledge and send the contents of the requested register. The transmission terminates when the master sends a Stop condition. If the master acknowledges the transmitted data byte, as in a Read Word command, the LTC4151/LTC4151-1 will send the contents of the next register. If the master acknowledges the second data byte |
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